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Design of a Low-power CMOS Level Shifter for Low-delay SoCs in Silterra 0.13 µm CMOS Process
Design of a Low-power CMOS Level Shifter for Low-delay SoCs in Silterra 0.13 µm CMOS Process
2017
Mohammad Torikul Islam Badal
Mamun Bin Ibne Reaz
Araf Farayez
Siti Aishah Ramli
Noorfazila Kamal
Keywords:
Logic level
Engineering
Electronic engineering
CMOS
low delay
cmos process
ultra low power
Correction
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