A wide band fractional-N digital PLL with a noise shaping 2-D time to digital converter for LTE-A applications

A wide band fractional-N digital PLL which uses a high resolution 2-dimension gated-Vernier time-to-digital converter (TDC) with 5.2 ps resolution is presented. The quantization noise shaping of the TDC greatly improves the in-band phase noise. While, in the same time, the 2-dimension structure makes the digital PLL (DPLL) be able to process large phase errors almost without the influence of latency time. Combined with a high figure-of-merit (FOM) class-D digitally controlled oscillator (DCO) and digital ΣΔ quantization noise cancellation based least mean square (LMS) algorithm, the DPLL achieves -110dBc/Hz and -140dBc/Hz for in-band and 10 MHz-offset phase noise, respectively, with carrier frequency of 3.5 GHz and 1 MHz bandwidth. The digital PLL is simulated in a 65 nm CMOS process, consuming 11.2 mW from a 1.0 V supply.