Reduced Instruction Set Computing.

Reduced instruction set computing (RISC) architecture started as a fresh look at existing ideas. The main featue of RISC is the architectural support for the exploitation of parallelism on the instruction level. All distinguished features of RISC should be considered in light of their support for the RISC pipeline. Keywords: IBM 801; RISC; computer architecture; load/store architecture; instruction sets; pipelining; superscalar machines; superpipeline machines; optimizing compiler; branch and execute; delayed branch; cache; Harvard architecture; delayed load; superscalar; superpipelined