Design and Implementation of a Low-Power Cyclic ADC for X-Ray Detector Readout Circuit

This paper describes a 12-bit 100KS/s cyclic analog-to-digital convertor (ADC) for X-Ray detector readout circuit implemented in SMIC 0.13μm CMOS process. The ADC adopted operational amplifier sharing technology to reduce the number of capacitance and operational amplifier. At different cycle stages, the gradually decreasing tail current of the op amp reduces the power consumption of the cyclic ADC. With the proposed clock, the kickback noise of dynamic comparator has no influence on sampling signal. The simulation result shows that the signal-to-noise-plus-distortion (SNDR) is 70.4dB, the spurious free dynamic rang (SFDR) is 84.2dB, the total harmonic distortion (THD) is -82.2dB, the effective number of bits (ENOB) is 11.39bit, and the power consumption of the ADC is 112μW.