Design and FPGA Synthesis of an Efficient Synchronous Counter with Clock-Gating Techniques

In the proposed work, we focused on clock-gating-based synchronous counter. This paper depicts the designing of high-speed synchronous counter with low dynamic power dissipation using clock-gating method. We study the various design technique to overcome the dynamic power dissipation in the synchronous circuit. After analysing the several techniques, we focused on clock-gating technique to minimize the dynamic power dissipation and compare the proposed counter to the previous counter in terms of latency, on-chip power dissipation, utilized area, and maximum operating frequency. The clock-gating technique enables for an improvement of 24, 36, and 31%, respectively, for latency, area, and maximum operating frequency as well as maintaining the on-chip power dissipation as the prior synchronous counter. The design proposal of 4-, 8-, and 16-bit synchronous counter is built by Verilog HDL code and synthesis is carried out with Spartan 3 FPGA on ISE design suit 14.2 Tool.