A 2.5 Mb/s, 23 mW SOVA traceback chip for turbo decoding applications

This paper presents a novel implementation of a low power architecture for the soft-output Viterbi algorithm (SOVA), a building block for turbo codes. The architecture builds on previous work on the Viterbi algorithm (VA) and SOVA, and incorporates a novel orthogonal access memory structure which allows received information to remain static while it feeds the underlying traceback pipeline. Ultimately, the work shows a feasible implementation of a 42-stage traceback pipeline for SOVA running with a traceback throughput of 7.5 Mb/s at 54 mW.