Optimal design and implementation of parallel VLSI circuits dedicated to image matching

This paper addresses the problem of architecture optimization, when implementing an image matching primitive in reconfigurable circuits. Circuit spatial organization is optimized in terms of processing time, and circuit volume, in order to suit well for real time on board applications. This optimized adaptive spatial and scalable organization of the (mu) PD circuit dedicated to image matching reduces by one order the spatial and temporal performance, without altering the quality of matching. The (mu) PD circuit has been validated with the minimal 22 elementary cells architecture with Xilinx 4010 XL circuit working at 12 MHz and occupying 92 percent of the circuit CLB. It performs the pyramidal 256 X 256 image matching in less than 1 s.