Plasma Etch Processes for Embedded FRAM Integration

We describe the etch processes used for integration of embedded ferroelectric random access memory (FRAM) within a standard CMOS logic flow. The ferroelectric module is inserted following front-end contact formation and prior to backend integration using only two additional mask levels: capacitor pattern and bi-level via pattern. The single-mask stack etch process employs a TiAlN hardmask to define Ir/IrOx/PZT/IrOx/Ir capacitors. Protective sidewalls can be formed using an etchback process. The bi-level via etch and subsequent metal fill processes complete the FRAM module formation. Functional 4 MB arrays embedded with 5 levels of Cu/FSG integration have been demonstrated.