GART (abstract): a new, flexible placement and routing tool for research on FPGA architectures

In this paper, we give an overview of the capabilities of GART (Generic Architecture Research Tool). This tool enables the user to research the effect of architectural parameters on the implementation of designs in different FPGA architectures. It allows the definition of, and the placement and routing of designs in a broad range of FPGA architectures. The graphical input format used for defining the target FPGA architecture and the associated placement and routing algorithms ensure a flexibility that surpasses comparable tools [1,2] by allowing (among others) direct connects, segmented routing structures, area-I/O and 3-D architectures. A preliminary evaluation of some example architectures containing direct connects is given to demonstrate the usefulness and the versatility of GART. The full paper will contain a more elaborate set of experiments.