Characterization of Substation Process Bus Network Delays

This paper presents the characterization of network delays in an IEC61850 process bus substation area network, both through theoretical analysis and simulations. Several design targets were defined considering the recommendations of standards and good design practices: number of network hops, total network delay, probability of the delay being exceeded, link load, network topology and availability. An analytical delay estimation methodology is proposed, considering both the steady-state traffic and traffic resulting from a breaker failure event. A complete substation is taken as an example for characterizing the network delays, considering a star network topology. Simulations allow to obtain the cumulative distribution functions and percentile values of network delays. Results show a good agreement between the simulation and the analytical analysis. While the delay is best characterized statistically through simulation, finding the maximum network delay through simulations can be very time consuming, making the analytical analysis more suitable.