Benchmarking and optimization of trench-based multi-gate transistors in a 40 nm non-volatile memory technology

This paper addresses the design and characterization of different architectures of novels high-density multi-gate transistors manufactured in a 40 nm embedded Non-Volatile Memory technology. The proposed multi-gate architectures are based on vertical transistors integrated in deep trenches built alongside the main transistor. Thanks to the built-in trench, the proposed manufacturing process increases the transistor width without impacting its footprint. The electrical behaviour of the different multi-gate transistor architectures is studied and compared based on I-V characteristics. Relevant physical and electrical parameters such as the device footprint, the ON and OFF currents along with the threshold voltage and subthreshold slopes are extracted in order to determine the best candidate among the three studied architectures.