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A Chip-ID Generating Circuit for Dependable LSI using Random Address Errors on Embedded SRAM and On-Chip Memory BIST
A Chip-ID Generating Circuit for Dependable LSI using Random Address Errors on Embedded SRAM and On-Chip Memory BIST
2012
Fujiwara Hidehiro
Yabuuchi Makoto
Nakano Hirofumi
Kawai Hiroyuki
Nii Koji
Arimoto Kazutami
Keywords:
Embedded system
Chip
Static random-access memory
Computer science
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