A 1V 15-bit Audio ΔΣ ADC in 0.18µm CMOS

In this paper a 1V 15-bit ΔΣ ADC for audio application is presented. Second order modulator with feed-forward path is adopted in order to reduce the swing of each integrator. Non-linear gain effect is mitigated. Single stage amplifier with high power efficiency is employed to save power. Decimation filter is implemented with seven-stage cascade sub-filters. Timing multiplexing and resource reuse methodology are employed for low hardware cost. The ADC is programmed to adapt 4K 8K 16K applications. Over 90dB SNDR performance can be achieved under various bandwidths while the total power dissipation is 360µW. The modulator occupies 0.3mm 2 and decimation filter occupies 0.2mm 2 .