Methods for reliably addressing a large flash memory

The invention relates to a flash memory on a host system (1) and a method thereof, with a controller (3), a volatile cache memory (4) and a plurality of erasable in an erase operation, the memory blocks, the memory blocks in memory pages are divided, which are in a write operation writable and each memory page is further divided into sub-pages, and each sub-page physical sub-page address (pua, pma) which, one from the host system addressable (1) logical sub page address (LUA, LMA) is associated, and the logical part of page addresses associated physical sub-page addresses by means of hierarchical structures of address tables (P, k, y; C, k, y) for the implementation of logical sub-page addresses (LUA, LMA) in physical sub-page addresses (pua, pma) are determined and the address tables, the have size of a memory page, wherein the plurality of memory blocks of the flash memory (2) in Areas is divided, the at least one static region (10) of described memory blocks, a write area (11), are written into the new and changed user data, a block management area (13) are stored in the management data to the memory blocks, and a logbook region include (12) and the physical sub-page addresses (pua) of the write area (11) of the logic part of page addresses (LUA) over a useful data address table structure (P, k, y), the physical part of page addresses (PMA) of the block management area (13) via a management block address table structure (C, k, y) can be determined and changes in the address tables in memory pages of the log area (12) are detectable.