Full-chip Inter-die Parasitic Extraction in Face-to-Face-Bonded 3D ICs

Face-to-face (F2F) bonded 3D ICs are promising design solutions. However, because of the short die-to-die distance, direct coupling between the metal layers of the top and bottom dies introduces severe signal integrity problems that call for accurate extraction. This study is the first to demonstrate and compare three parasitic extraction methods of F2F-bonded 3D ICs. One is traditional die-by-die extraction, which cannot handle inter-die coupling and E-field sharing. We propose another method, holistic extraction, which treats all layers from both dies simultaneously and captures all inter-die coupling at the cost of high Layout Versus Schematic (LVS) complexity. We also propose an in-context extraction method that accounts for interface layers between dies. Carefully handling double-counting and surface layers issues, in-context extraction is LVS-friendly without losing accuracy. Full-chip analyses show that both of our extraction methods are highly accurate and able to handle various metal layers in several process nodes. It also corrects timing, power, and signal integrity errors introduced by die-by-die extraction. In-context extraction with two interface layers is highly accurate and efficient with an error of 0.9% for total ground capacitance and 0.8% for total coupling capacitance.