CMOS compatible process for suspended high-aspect-ratio integrated silicon microstructures

A CMOS compatible process for fabricate high aspect ratio integrated silicon microstructure which provides a possibility of bulk integrating micromachining with CMOS circuit on a chip. The MEMS structures is fabricated on the same substrate of their interface CMOS circuits and electrically isolated from the circuits by trenches which promises to enhance the system performance as well as lower the packaging cost of micromachining inertial devices. The residue silicon was removed before structure releasing with selected area anisotropic etching. The electrical characteristics of the transistors with MEMS fabrication agrees well with those without MEMS fabrication.