Multi-core program determinacy replay-facing memory competition recording device and control method thereof

2012 
The invention discloses a multi-core program determinacy replay-facing memory competition recording device and a control method thereof, and relates to a memory competition recording device, in order to solve the problem that a memory competition recording method is high in cost. The memory competition recording device is a multi-core processor system based on a Cache coherence protocol, and records the memory competition when a multi-core program operates, wherein the recording method records an indirect dependency represented by present instructions of processor cores of both rival parties when the competition occurs, instead of directly recording the dependency corresponding to the memory competition, so as to record a memory competition log composed of the indirect dependencies for each thread; the indirect dependencies of the memory competition are recorded to store a segment timestamp with a smaller size for each instruction without storing an instruction count value corresponding to the memory operation instruction for each memory block. Meanwhile, the reduction of the memory competition log is realized by using a segmentation method, and the consumption of hardware resources is greatly reduced. The invention is used for multi-core program debugging, intrusion detection and fault tolerance.
    • Correction
    • Source
    • Cite
    • Save
    • Machine Reading By IdeaReader
    2
    References
    0
    Citations
    NaN
    KQI
    []