A Highly Parallel Single Chip Video signal Processor

Publisher Summary Software-implementation of complete image processing tasks is quite demanding. Yet, none of the VSPs proposed so far is supported by a compiler enabling parallel programming in a high level language. The envisaged image processing system has small volume and low power dissipation—that is, being based on very-large-scale integration (VLSI) video signal processors. These processors must be capable of achieving a high sustained performance over a wide range of image processing algorithms. Because image processing applications are growing in complexity, the processor must be programmable in high level languages supporting parallelization. This chapter presents a video signal processor (VSP) that fulfills the named goals. A parallel VSP's processing power is determined by the number of operations executed concurrently and the cycle time per operation. Therefore, the chapter provides a single instruction stream; multiple data stream (SIMD)-architecture that avoids the large overhead introduced by separate control-units per processing unit and consequently, achieves a high parallelism. Highly parallel single-chip video signal processor architecture has been inferred by analysis of image processing algorithms. Available levels of parallelism and their associated demands on data access, control, and complexity of operations have been taken into account. The architecture consists of a reduced instruction set computing (RISC) style control unit with separate instruction cache, 16 parallel data paths with local data caches, a shared memory with matrix type data access, and a powerful direct memory access (DMA) unit. Multi-processor systems are supported by four hypercube links with auto-routing capability. A C++-Compiler and an optimizing assembler have been implemented, fully supporting all levels of concurrency. The processor achieves a very high sustained performance for a broad spectrum of image processing algorithms.