A 28-nm 1R1W Two-Port 8T SRAM Macro With Screening Circuitry Against Read Disturbance and Wordline Coupling Noise Failures

We demonstrate a 1-read/1-write two-port (2P) embedded static random access memory macro based on 8T SRAM bitcell with an effective scheme for design of testability. To achieve a smaller macro area, a differential sense amplifier is introduced to read out the data, where the reference voltage for reading 0/1 data is generated by an unselected bitcell array. In addition, we propose a screening test circuit for read disturbance and wordline coupling noise. A 512-kbit 2P SRAM macro using 28-nm high-K/metal gate bulk CMOS technology has been designed, confirming experimentally that the worst minimum operation voltage ( $V_{\text {min}}$ ) can be reproduced by our test circuit. Bit density of 3.16 Mb/mm 2 was achieved.