Impact of boron penetration at the p/sup +/-poly/gate-oxide interface on the device reliability of deep submicron CMOS logic technology

Impact of boron penetration at the p/sup +/-poly/gate-oxide interface is investigated. It is shown that the onset of boron penetration at this interface can not be detected by conventional threshold or flatband voltage shifts of p-channel devices, but it results in significantly lower Q/sub BD/ and Vt instability. Constant current stress in inversion has been found to be most sensitive technique to monitor the onset of boron at the p/sup +/-poly/gate-oxide interface.