Design and implementation of a CFAR processor for target detection
2004
Real-time performance of adaptive digital signal processing algorithms is required in many applications but it often means a high computational load for many conventional processors. In this paper, we present a configurable hardware architecture for adaptive processing of noisy signals for target detection based on Constant False Alarm Rate (CFAR) algorithms. The architecture has been designed to deal with parallel/pipeline processing and to be configured for three versions of CFAR algorithms, the Cell-Average, the Max and the Min CFAR. The architecture has been implemented on a Field Programmable Gate Array (FPGA) with a good performance improvement over software implementations. Results are presented and discussed.
Keywords:
- Field-programmable gate array
- Hardware architecture
- Signal processing
- Adaptive algorithm
- Constant false alarm rate
- Digital signal
- Real-time computing
- Digital signal processing
- Embedded system
- Architecture
- Distributed computing
- Computer science
- Signal-to-noise ratio
- Computer hardware
- Performance improvement
- Circuit design
- Correction
- Cite
- Save
- Machine Reading By IdeaReader
0
References
1
Citations
NaN
KQI