Using soft processors for component design in SOC: A case-study of timers

System on Chip (SOC) could be considered as a very useful alternative in the design of real-time systems, especially due to the possibility of integrating several processors in just one FPGA. This strategy enables the use of soft processors to design the systempsilas components, which have traditionally been developed by hardware. In this paper we study a HW/SW codesign of a timer pool for its use in SOC, which is constructed by a Picoblaze soft processor. Our approach offers a novel alternative among hardware and software timers that increases the overall system performance, and achieves a higher precision than software timers with a considerable reduction in cost and area occupied.