Novel Thin Sidewall Structure for High Performance Bulk CMOS with Charge-Assisted Source-Drain-Extension

We have developed a novel junction profile engineering using thin sidewall structure and applied it to sub-40 nm uniaxial strained CMOS devices. This transistor used a high-k thin sidewall with electrical charge in achieving a higher drive current with keeping the short channel effect. Consequently, the 18.5/15.6% reduction of parasitic resistance achieve the 8.2/13.0% improvement in the saturation current (I on ) at 38 nm gate length for nMOS and pMOS. In addition, I on dependence on active width (W g ) for pMOS is very small. In the size of active width : 0.1 mum, a 42% of I on enhancement gave us I on = 680 muA/mum at V dd =1 V. These characteristics are originated from formation of inversion layer and suppressing channeling penetration of pocket impurities implanted. A high performance Bulk nMOS and pMOS were demonstrated with I on of 1069 muA/mum and 725 muA/mum at V dd =1 V / I off =100 nA/mum, respectively.