An integrated FIR adaptive filter design by hybridizing canonical signed digit (CSD) and approximate booth recode (ABR) algorithm in DA architecture for the reduction of noise in the sensor nodes

The Finite Impulse Response (FIR) filter plays an important role in many signal processing applications. This manuscript proposes an intuitive adaptive filter based on fixed-point finite impulse response with approximate distributed arithmetic (DA) circuits. For digital signal and image processing requirements, several floating-point multiplications are mandatory. The floating point multiplication is implied by the canonically signed integer (CSD) and contrasts with the conventional multiplication technique. Moreover, a new multiplier method is introduced that translates 2's supplement into CSD in real time. The Booth algorithm is a multiplication algorithm that uses two additional notations of signed bits to multiplier multiplication. The Booth approach allows the count of partial products (PPs) to be diminished efficiently through categorizing consecutive bits to the multitude of signed multiples as one of the operands. The operand encoded by Booth is known as the multiplier and the other operand is called multiplicand. By incorporating the CSD and approximate booth recode (ABR) number representation in the multiplier and improving multiplier output and energy consumption the number of non-zero components is minimized. An intensive DA-based approach is proposed on the technology based on an exact and optimized dispersed arithmetic, which reconfigures finite impulse response filters, whose filter coefficients transition in runtime. The algorithm of this prototype is used to restrict the number of component DA products with the CSD and ABR, although there is no explicit multiplication. The partial products are provided by decreasing data input by offsetting errors. A wallace tree is known for its partial product accumulation that reduces the cost of hardware. The proposed hardware design reduces partial non-zero products to minimum and restricts the number of arithmetic operations in the carrying saved device. The proposed architectural framework is implemented in Verilog with a Xilinx 14.5 ISE simulation. Utilization of hardware is reduced and also critical path delay of the propose architecture is reduced to 5 s. Maximum operating frequency of the proposed architecture is 126.9 MHz. The experimental results demonstrate that the proposed motion estimation algorithm has better performance likened to the existing works.