Characterization and physical modeling of the temporal evolution of near-interfacial states resulting from NBTI/PBTI stress in nMOS/pMOS transistors

The last decade of BTI research has seen a frantic search for ultra-fast measurement methods to correctly understand the impact of fast as-grown traps which impact the initial phase (1 ks) of the degradation and recovery. These methods focus mostly on determining the time-dependence of the threshold voltage shift. Other experimental methods able to resolve the energetic distribution of traps in the bandgap have recently not been as frequently employed as they introduce a large delay and also require switching the device into accumulation, which considerably accelerates recovery. Here we use detailed CV measurements to study NBTI/PBTI in SiO 2 nMOS/pMOS capacitors. We extract a unique defect band inside the SiO 2 insulator which can describe the build-up of near-interfacial states over time in all four combinations using our recently suggested gate-sided hydrogen release model. Our results suggest that depending on the transistor type and stress bias conditions, the generated slowly-recovering near-interfacial states are due to a combination of slower oxide traps and faster P b centers.