Wafer edge protection kit for MEMS and TSV Si-etching

A new process kit for a SPTS Pegasus DRIE Si-Etch tool has been developed and tested for several different process regimes, e.g. bulk-Si cavity etching and TSV (through-Silicon-Via) etching with high aspect ratios 2 O 3 material and optionally of PEEK material, covers the edge of a wafer, preventing it from being etched or even being etched away. However, placing such a part on top of the cathode, results in changes of the electric field distribution and the gas flow behavior compared to the standard process kit supplied by SPTS. The consequences may be altered Si-etch rates combined with changes of the tilt and side wall taper of the etched structures, mainly near the outside regions of the wafer. To this end, extensive investigations on the mask and bulk-Si etch rates, the tilt and taper angle of various MEMS test structures and their respective uniformity over the wafer surface have been performed. Additionally, simulations applying Comsol Multiphysics have been carried out to visualize the potential impact of the new process kit on the electrical field distribution. A simplex-optimization was carried out, varying the platen power and source power, in order to improve the tilt and to maintain the proper taper angle. One major advantage of the new process kit design compared to the original one is the reduction of movable parts to a minimum.