BiCMOS approach for a RISC microprocessor

A concept for a BiCMOS implementation of a reduced-instruction-set-computer (RISC) microprocessor CPU is proposed. It is based on a CMOS implementation without architectural changes to maintain software compatibility. The circuit paths are analyzed and the provisions for special functional units such as the cache, data path, and internal memory are derived. A performance gain factor of 2.5 was achieved with a limited number of bipolar current switches, and, in contrast to pure emitter-coupled-logic (ECL) solutions, extensive use of ECL in the 32-bit-wide data path is avoided. The appropriate strategy for BiCMOS logic circuitry is to limit the use of the bipolar current switches (ECL) to time-critical paths and to leave the bulk of the circuitry such as memory cell arrays and less time-critical functions in CMOS. >