A Configurable Asynchronous Pseudorandom Bit Sequence Generator

We present a method of building pseudorandom bit sequence (PRBS) generators using coupled asynchronous FIFO rings. A traditional PRBS generator using a linear feedback shift register (LFSR) can only generate a single maximal-length pattern with a fixed period. Our proposed FIFO implementation allows a single circuit to produce many different patterns of different periods, all of which are maximal-length, based on the initialization of the circuit. It also provides intrinsic fine-grain pipelining which alleviates the large feedback logic overhead in configurations with many taps, making such implementations practical. With an asynchronous-to-clocked interface, one can use the circuit in a synchronous environment. Detailed simulation results are presented.