Ultra-Short-Reach Interconnects for Die-to-Die Links: Global Bandwidth Demands in Microcosm

To meet the ever-increasing demand of global data traffic, the Hybrid Memory Cube (HMC) specification and High-Bandwidth Memory standard call for an aggregate bandwidth of 8 Tb/s in next-generation memory-to-processor links [1], [2]. At the same time, the data rates processed by individual line cards in data center switches will soon go beyond 25 Tb/s [3]. However, as the data rate of serial links over copper interconnects increases, the links appear highly lossy. Further, the power consumption of a wireline transceiver, including all clocking and equalization circuits, increases. Publications suggest a tenfold increase in power consumption with a 30-dB increase in channel loss [4]. Hence, energyefficient communication equipment should be engineered to keep the channel loss as low as possible.