Etude des propriétés électriques d’empilements high-K/grille métal en vue de leur intégration dans les dispositifs CMOS-sub 45 nm

This work concerns the study of electrical properties of advanced transistors integrating High-KImetal materials. We addressed in a first part, the basic characterization of these stacks especially EuT thermal star first-level defects characterization and conduction analysis. We are also interested in electrical defects resultin! phenomenon named Positive Bias Temperature Instability (PB TI). To make an intensive investigation of parasitic effect, we have introduced a new time resolved characterization technique evidencing different categ of PBTI defects depending on reversible or irreversible behavior. Afterwards, we focused on the modelir reversible traps. After an accurate identification of charging and discharging mechanisms, a SRH model led extract traps physical properties. Finally, we have investigated another phenomenon resulting in an uncontr flat band voltage with an electrical and optical technique based on InternaI Photo-Emission.