Integrated circuit and preparation method thereof

The invention relates to an integrated circuit comprising an integrated circuit substrate, a low-dielectric constant material layer, a barrier layer and a copper layer. The low-dielectric constant material layer is arranged at the surface of the integrated circuit substrate; and at least one groove is formed in the surface, far away from the integrated circuit substrate, of the low-dielectric constant material layer, wherein the depth of the at least one groove is less than that of the low-dielectric constant material layer. The copper layer is arranged in the at least one groove. The barrier layer arranged in the at least one groove is located between the copper layer and the inner wall of the groove and is a silanization self-assembled monolayer that is formed by 3-(2-aminoethyl)-aminopropyl trimethoxy silane or (3-mercaptopropyl) trimethoxy silane. In addition, the invention also provides a preparation method of the integrated circuit.