Circuit-Level Techniques to Mitigate Process Variability and Soft Errors in FinFET Designs
2019
The yield optimization and radiation hardness are relevant reliability requirements as chip manufacturing advances more in-depth into the nanometer regime. One way to obtain improvements in these issues is by applying techniques to mitigate the effects of process variability and radiation-induced soft errors in the circuits. This work reports the use of three circuit-level approaches in FinFET designs as well as point out the pros and cons of adopting it.
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