Low-dielectric constant materials 3. Materials Research Society symposium proceedings Volume 476

Continuing improvement of integrated circuits (ICs) critically depends on the use of nonconventional materials. Interconnect delay is already the most severe limiting factor in most advanced ICs. This delay can be minimized by reducing the interconnect capacitance, which is determined by a combination of process architecture and materials. While a broad range of candidate materials is being explored for IC application, there is no clear consensus on what material will be used to replace SiO{sub 2}. Process architectures are also unsettled, with various efforts directed at either evolving present-day technology or switching to a damascene metal approach. yet these processes may not be scaleable beyond the 0.15 {micro}m generation of IC technology. Thus, there still exists a need for basic understanding of interconnect materials and the limits of interconnect technology. This volume, the third in a series from MRS, brings together experts in the field of low-k dielectrics to focus on the challenges ahead. Topics include: organic and inorganic dielectrics; interfaces and porous materials; measurement and characterization; vapor-deposited materials; fluorinated oxides and polyimides.