Novel procedure to improve LDMOS ESD characteristics by optimizing drain structure

Novel procedure to realize a high ESD robustness with small variation for 40V p-ch LDMOS is proposed. By optimizing the drain structure, current flow path detaches from highest electric field point during ESD events, which leads to improve both HBM robustness and its variation. By using this procedure, the device length (the length between drain and source contact) increase could be suppressed from 37 % to 8 % compared with another approach which introduced ballast resistance in the drain. The studied 40V p-ch LDMOS achieved over 6200 V HBM performance keeping the drain-source breakdown voltage (|BVdss|) over 46 V.