Enhanced Limited Magnitude Error Correcting Codes for Multilevel Cell Main Memories

Technological advancements in emerging non-volatile memory (e.g., phase change memories) has led to viable alternative solutions to problems faced by technology scaling of conventional memories. Phase change memories suffer from the issue of resistance drifts wherein the value stored changes by a limited magnitude. Decimal arithmetic based limited magnitude Orthogonal Latin Square codes have been recently proposed to correct multiple errors based on asymmetric limited magnitude error models. This research letter proposes an additional technique which is combined with the decimal arithmetic based Orthogonal Latin Square codes previously proposed. This combined approach is shown to further reduce the data redundancy without incurring any significant penalty in terms of area and latency of the decoding and encoding circuit.