Design and Implementation of a 32-Bit Incrementer-Based Program Counter

The paper presents the design and implementation of a 32-bit program counter that has been used in DLX-RISC processor which uses Tomasulo Algorithm for out of order execution and a 32-bit program counter based on incrementer logic that was self designed on Virtex-7 FPGA board. The results for power, delay, and area were compared in order to obtain optimal results for the program counter. The power delay product (PDP) of the program counter design based on incrementer logic was found to be 94.4% less than that of the program counter used in DLX-RISC processor. Thereby, the improvised program counter enhances the overall performance of any processor it is used in as the power and delay have been substantially reduced in the proposed design. The designs are simulated and synthesized on Xilinx Vivado 2015.4 using VHDL and are implemented on Virtex-7 FPGA.