A highly scalable parallel spike-based digital neuromorphic architecture for high-order fir filters using LMS adaptive algorithm
2019
Abstract This brief presents a highly scalable parallel neuromorphic architecture to efficiently compute high-order adaptive FIR filters using a least mean square (LMS) algorithm. This has been achieved by eliminating critical paths because they critically affect the scalability of advanced parallel architectures. Here, the scalability is defined in terms of number of taps and bit-length. On the computation of high-order adaptive FIR filters, the multiplication is the most demanding operation. Therefore, we have made intensive efforts to create a compact new neural multiplier by improving the design and hardware implementation of an existing neural multiplier. The resulting multiplier requires 50 % fewer synapses, 40 % fewer neurons, 30 % fewer area resources and 26 % fewer clock cycles compared with the existing neural multiplier, respectively. The efficient implementation of the proposed multiplier has allowed us to eliminate critical paths significantly and thus the bit-length can be easily increased to guarantee the convergence performance when high-order adaptive filters are processed. To demonstrate its effectiveness, the proposed multiplier was included in the neuromorphic architecture to support high-order adaptive FIR filters. In addition, we employ the time multiplexing technique to maximize the utilization of the proposed neural multiplier by performing filter processing and the adaptive process because multiplication is involved in both. We mainly use this strategy to eliminate critical paths and reduce the area consumption by implementing a large number of taps. The proposed neuromorphic architecture was implemented on the Kintex-7 Field Programmable Gate Array (FPGA) development kit to validate its performance. Our results demonstrate that the neuromorphic architecture is capable of processing higher adaptive FIR filters compared with previously reported solutions. This potentially allow its practical use in many advanced digital signal processing applications such as acoustic echo cancellers, active noise control, channel equalization and system identification.
Keywords:
- Field-programmable gate array
- Adaptive algorithm
- Machine learning
- Real-time computing
- Scalability
- Artificial intelligence
- Architecture
- Digital signal processing
- Multiplexing
- Adaptive filter
- Mathematics
- Neuromorphic engineering
- Least mean squares filter
- Multiplier (economics)
- Pattern recognition
- Computer hardware
- Finite impulse response
- Correction
- Source
- Cite
- Save
- Machine Reading By IdeaReader
42
References
7
Citations
NaN
KQI