Design and implementation of low power reservation station of a 32-bit DLX-RISC processor

This paper presents the implementation of a reservation station used in a 32-bit DLX RISC processor using Tomasulo algorithm on 20nm and 28nm FPGA boards and compares the results for power, delay and area. The algorithm is a computer architecture hardware algorithm for dynamic scheduling of the instructions that allows out-of-order execution. This design helps utilize multiple execution units more efficiently. The Reservation Station is the heart of Tomasulo algorithm and is responsible for out-of-order execution. The design is simulated and synthesized on Xilinx Vivado 2015.4 using VHDL and is implemented on Kintex Ultrascale and Virtex 7.