Electrode/oxide interface engineering by inserting single-layer graphene: Application for HfO x -based resistive random access memory

Electrode/oxide interface with inserted single-layer graphene (SLG) increases low resistance state (LRS) resistance (> 1MΩ) due to its intrinsically high out-of-plane resistance in HfO x -based resistive random access memory (RRAM). This interface engineering technique enables the reduction of the RESET current by 22 times and the programming power consumption by 47 times. The interface between oxide layer and metal electrode is studied using Ramen spectroscopy coupled with electrical measurement. Raman mapping and single point measurements show noticeable changes in both D-band and G-band signals of SLG during electrical cycling. This observation suggests a possible interaction of oxygen migrated from the metal oxide with the graphene. This work illustrates that interface engineering design plays an important role for RRAM material selection in addition to exploring different metal oxides or metal electrode materials for RRAM.