Old Web
English
Sign In
Acemap
>
Paper
>
Signal integrity and timing issues of VME64x double edge cycles
Signal integrity and timing issues of VME64x double edge cycles
2005
Aloisio
Branchini
Cevenini
Izzo
Loffredo
Lomoro
Keywords:
Signal timing
Data acquisition
Synchronization
Electronic data interchange
double edge
bandwidth
Computer hardware
Signal integrity
ansi standards
Computer science
Correction
Source
Cite
Save
Machine Reading By IdeaReader
0
References
0
Citations
NaN
KQI
[]