A 2 Kbit Memory Array of Mixed-V T GC-eDRAM Implemented in 130nm Standard CMOS Technology

The minimization of very large-scale integrated circuits is facing a great challenge as the demands of devices with low power, and high-performance characteristics have intensely increased. Achieving a downscaled embedded memory design with a low leakage power, high stability, and minimized area became harder to achieve with SRAM based memories. A memory structure which is of great interest is the Gain-Cell eDRAM (GC-eDRAM). It has a high density, low leakage, logic compatibility, and suitable for two-port operations. This work presents a novel cell topology of mixed- $\boldsymbol{V_{T}}$ 3T GC-eDRAM to improve the data retention times (DRT) and speed for better energy efficiency in embedded memories. Simulations work is conducted to evaluate the performance of a 2 Kbit mixed $-\boldsymbol{V_{T}}$ 3T GC-eDRAM array layout until corner process simulation. Mentor Graphics Software is used to design and simulate each of the block diagrams in 130nm CMOS process technology. The array demonstrated successful operation at 400Mhz under a 1V supply and is almost 60-75% less in area than 6T SRAM in the same technology. The retention power showed about 80-90% lower power consumption as compared to the existing 6T and 4T ULP SRAMs (others‘ work).