FPGA hardware accelerator for holographic memory calculations for optically reconfigure gate arrays

Radiation-hardened optically reconfigurable gate arrays have been developed for use in space embedded systems. An optically reconfigurable gate array consists of a holographic memory, a laser array, and an optically reconfigurable gate array VLSI, which is one type of radiation-hardened SRAM-based field programmable gate array (FPGA). However, optically reconfigurable gate arrays have the important feature of faster scrubbing operations than that of radiation-hardened SRAM-based FPGAs. Therefore, the soft-error-tol er anees of the configuration memories of optically reconfigurable gate arrays become much higher than those of FPGAs. However, the calculation load of a lot of holographic memory patterns on a personal computer is extremely heavy. This paper therefore presents a hardware accelerator using an FPGA. The Vivado-high-level synthesis tool (Xilinx Inc.) has been used for development. Its operation speed was improved drastically from 1,590 ms to 3.12 ms while its power consumption for calculations has been decreased drastically from 55 W to 4.4 W.