Extended analysis of SSN effect on phase-locked loop (PLL) circuit

Electronic devices are increasingly susceptible to simultaneous switching noise (SSN) as devices shrink in size and operate at lower voltage to achieve higher speed. This is a major concern in high-speed system designs as SSN causes voltage and timing variations which affect signal integrity. Consequently, it is imperative that electronic system designers pay strict attention to signal integrity whether it is on the chip level or on the system level. This paper analyzes the output buffer SSN effect on the phase-locked loop (PLL) input pins, PLL output pins, and PLL power supplies using an Altera FPGA device. Experimental results show that direct PLL jitter transfer principle cannot be applied in a straight forward manner because of the wide spectrum and asynchronous nature of SSN. However, the PLL circuit is still effective in filtering the noise that is attacking the PLL input signal. This paper also shows that SSN greatly affects the PLL power distribution network (PDN) especially when the noise coupled into the PDN have the same frequency as the PDN resonance. In addition, it is also shown that SSN do not directly attack the PLL circuit through its output. These findings assist Altera's customers and electronic system designers in optimizing PLL performance for error-free device designs. Furthermore, the findings provide a basis future PLL design improvements.