Hardware Support for Cost-Effective System-Level Protection in Multi-core SoCs

The increasing adoption of multi-core Systemson-Chip (SoC) in critical systems has turned security into an important design requirement. In addition to making a SoC tamper-resistant by embedding cryptographic solutions, in order to make a system robust, we need to control the level of access to the critical functions and capabilities. We propose a hardware protection architecture to enhance a traditional SoC platform in terms of protection. These hardware enhancements focus on isolating physical memory compartments by applying access rules, thus we allow dynamic security policies to be enforced at the hardware for protection against untrustworthy hardware or software components. We present and analyze an implementation of a prototype that allows sixteen concurrently active protection domains at a system cost of less that three percent and negligible operational overhead.