A low power and ultra high reliability LDPC error correction engine with Digital Signal Processing for embedded NAND Flash Controller in 40nm COMS

A multi-mode Low-Density Parity-Check (LDPC) error correction engine with a Digital Signal Processing (DSP) module is presented for low power and ultra high reliability NAND Flash memory controllers. The DSP module improves the reliability of the storage systems via calculating the adaptive reliability information and translating the information into Log-Likelihood Ratio (LLR) for soft bit decoding. According to the experiment results on sub-20nm Triple Level per Cell (TLC) NAND Flash memory, the retention ability of LDPC with DSP is a 20 times improvement over BCH code and 2 to 5 times improvement over conventional LDPC. Moreover, the proposed decoder reaches a throughput over 400MB/s as well as a power consumption of 21.8mW under 40nm CMOS technology at 45 bit errors.