High quality Ta/sub 2/O/sub 5/ gate dielectrics with T/sub ox.eq/<10 /spl Aring/

High quality Ta/sub 2/O/sub 5/ gate stack with T/sub ox,eq/=9 /spl Aring/ (measured @ Vg=-2.5 V in strong accumulation without taking quantum mechanical effects into account) and the leakage current Jg=0.19 A/cm/sup 2/ @ Vg=-1.0 V has been achieved using NH/sub 3/-based interface layer, H/sub 2//O/sub 2/ post-deposition anneal and TiN diffusion barrier. The leakage current of Ta/sub 2/O/sub 5/ gate stack with NO interface layer is 10/sup 4/x lower than that of RTP SiO/sub 2/ with same T/sub ox,eq/ and can be further reduced by a factor of 100 with NH/sub 3/-based interface layer.