Protected And Valuable Cutting For Packet Classification

Hardware implementations of Internet Protocol (IP) classification algorithms have been proposed by the research community over the years to realize high speed routers and Internet backbone. Abstract— Decision-tree-based packet classification algorithms such as HiCuts, HyperCuts, and EffiCuts are most popular classificasion these are  show excellent search performance by exploiting the geometrical representation of rules in a classifier and searching for a geometric subspace to which each input packet belongs. However, the primary challenge in implementing this high-level approach lies in the second phase, i.e. how to efficiently combine the results of the single field searches. In this paper, we propose a systolic-array-based architecture on FPGA focusing on the combining techniques in phase two. Classification techniques  approach exploits the rich logic resources on FPGA and achieves high throughput by deeply pipelining the architecture. We show the area analysis of the design to demonstrate the efficiency in on-chip resource usage. The system will present experimentally evaluate the impact of the size of the input ruleset and number of matching rules from first phase on the performance of our design. Hence, the cutting in the proposed algorithm is deterministic rather than involving the complicated heuristics, and it is more effective inproviding improved search performance and more efficient in memory requirement.