Local loops for robust inter-layer routing at sub-20 nm nodes

As the metal pitch continues to shrink, it becomes inefficient, if not impossible, to use traditional via redundancy schemes at and below the 14 nm node. Double-cut vias and via bar connections will either block many adjacent routing resources or make it impossible to pattern at these advanced technologies nodes. In this paper we examine a scalable via redundancy strategy based on local loops. We evaluate the yield and timing impact of local loops and use a 14 nm standard cell library and functional block designs to assess the design cost of local loops. Furthermore, lithography contours and process window simulations are used to demonstrate the manufacturability of this structure. With supporting EDA tools and design-technology co-optimization (DTCO), local loops will become an important via redundancy topology at sub-20nm nodes.