Dominant four-pole placement in filtered PID control loop with delay

Abstract The paper proposes a novel approach to the filter design in the delayed PID control loop. The novel approach is based on the dominant four-pole placement providing all five controller parameters including the filter time constant and damping factor. Moreover, the dominant four-pole placement is carried out iteratively as long as an optimum dominant four-pole placement is achieved by means of the constrained IAE optimization. The constraints considered for the optimization are the dominance of the placed poles and the fixed value of the filter damping factor. The achieved optimum dominant four-pole placement then corresponds to the least IAE obtained under these constraints. Then the filtered PID controller results very close to the ideal PID controller up to the filter cut-off frequency. Finally, the constrained IAE optimization of the disturbance rejection is preferred in the paper.