High-speed Sensing Techniques for

Two high-speed sensing techniques suitable for ultrahigh-speed SRAM's are proposed. These techniques can reduce a 64-kb SRAM access time to 71 - 89% of that of con- ventional high-speed bipolar SRAM's. The techniques use a small CMOS memory cell instead of the bipolar memory cell that has often been used in conventional bipolar SRAM's for cache and control memories of mainframe computers. There- fore, the memory cell size can also be reduced to 26 - 43% of conventional cells. A 64-kb SRAM with one of the sensing tech- niques is fabricated using 0.5-pm BiCMOS technology and achieves a 1.5-11s access time with a 78-pm2 memory cell size. The techniques are especially useful in the development of both ultrahigh-speed and high-density SRAM's, which have been used as cache and control memories of mainframe computers. I. INTRODUCTION LTRAHIGH-speed bipolar SRAM's have continued to enhance the performance of mainframe com- puters. This is because the feature of bipolar SRAM's, that is, high speed, is especially suitable for cache and control memories in mainframe computers. Under such circumstances, ultrahigh-speed 32 - 64 kb bipolar SRAM's with access times in the range of 1.5 to 2.5 ns have been proposed (1)-(6). In these SRAM's, Schottky-clamped bipolar memory cells were often used to achieve high-speed access times. However, it has be- come increasingly difficult to decrease the memory cell size of these SRAM's only by decreasing the device sizes, because the number of devices which compose the mem- ory cell is large. Moreover, further reduction in access time is also difficult with these memory cells because a large bit-line current is needed to decrease the delay times of the cell and sense circuit. This large bit-line current requires a large emitter size and wide bit-line width of the memory cell, which conflicts with the smaller cell size. Therefore, new SRAM technology is necessary to obtain SRAM's with higher speed and density.